I had a case where I was getting load verify errors when going to debug mode on a SiLabs EFM32GG11 processor using a SiLabs STK JTAG interface with Segger JLink on it for programming.
I narrowed it down to changing one include of about 100 lines of source. Compiling with version A of the code would work and compiling with version B would give a 'Verify Error' failure. This is after swapping STK's, cables, computers and versions of JLink over a three day period.
Then I tried loading the code with version 6.34 of Jlink in Rowley and also in SiLabs Simplicity Commander. I found the failure was specific to Rowley only.
So I tried Target->Verify File on Rowley and I found that if I verified the .elf file it would fail and if I verified the .bin file it would fail, but if I then went back and debugged again, the debug load would succeed. And keep succeeding.
Curiously, somewhere in the middle of all that I did a verify of what was in the EFM32 processor against a binary from earlier in the day and while the debug load verify failed the 'target->verify file' against the older image succeeded.
So it seems there is an issue with compare image sometimes being wrong when the Rowley IDE goes to debug and the 'target->verify file' against a different image type seems to be a workaround.
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