TCP/IP Library and RMII

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Mjscott

• April 01, 2014 12:55

In the Docs and examples it seems like the hardware (for the STM32) is only setup for MII, however the board I designed uses the interface as RMII. The difference is basically 2 data bit vs 4 and a 50Mhz native clock vs 25, basically an Ethernet interface with the lowest number of connections between the interface and PHY. There isn't a lot of info on hardware initialization, can you supply something? or an example of RMII initialization?

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• 

  Paul Curtis

  • April 04, 2014 12:40

  Many of the board support packages for STM32 are in RMII mode, the STM32 "-EVAL" boards are different in that default shipping condition is MII mode.

  Take, for instance, the Olimex STM32-E407 initialization, which is presented below.

  /* $(LICENSE)
  */
  
  #include "libplatform/platform.h"
  #include "libplatform/platform_heaps.h"
  #include "libplatform/platform_stm32f4.h"
  #include "libplatform/platform_private.h"
  #include "libnet/designware_emac_v3.h"
  #include <ctl_api.h>
  #include <stm32f4xx.h>
  
  static const PLATFORM_PIN_CONFIGURATION_t emac_configuration[] =
  {
    { STM32_E407_RMII_REFCLK, PIN_FUNCTION_ETHERNET_INPUT  | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_MDIO,   PIN_FUNCTION_ETHERNET_OUTPUT | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_MDC,    PIN_FUNCTION_ETHERNET_OUTPUT | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_CRS_DV, PIN_FUNCTION_ETHERNET_INPUT  | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_RXD0,   PIN_FUNCTION_ETHERNET_INPUT  | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_RXD1,   PIN_FUNCTION_ETHERNET_INPUT  | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_TXD0,   PIN_FUNCTION_ETHERNET_OUTPUT | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_TXD1,   PIN_FUNCTION_ETHERNET_OUTPUT | PIN_CLAIM_LOCKED },
    { STM32_E407_RMII_TXEN,   PIN_FUNCTION_ETHERNET_OUTPUT | PIN_CLAIM_LOCKED },
    { PLATFORM_END_OF_LIST, 0 }
  };
  
  CTL_STATUS_t
  stm32f4_emac_start(CTL_NET_INTERFACE_t *self)
  {
    CTL_STATUS_t stat;
    CTL_TIME_t t0;
  
    // Enable clocks for Ethernet peripheral, but not for PTP.
    RCC->AHB1ENR |= 1*RCC_AHB1ENR_ETHMACEN |
                    1*RCC_AHB1ENR_ETHMACTXEN |
                    1*RCC_AHB1ENR_ETHMACRXEN |
                    0*RCC_AHB1ENR_ETHMACPTPEN;
  
    // Select the RMII interface.  The STM32F1 manual says that this must
    // be performed whilst the module is under reset and before enabling
    // the MAC clocks...
    SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
  
    // Reset Ethernet peripheral on AHB bus.
    RCC->AHB1RSTR |=  RCC_AHB1RSTR_ETHMACRST;  // Apply reset
    RCC->AHB1RSTR &= ~RCC_AHB1RSTR_ETHMACRST;  // Release reset.
  
    // Request software reset: resets all MAC internal registers and logic.
    // After reset, all registers hold their reset values.
    ETH->DMABMR |= ETH_DMABMR_SR;
  
    // Wait for software reset to complete.
    t0 = ctl_get_current_time();
    for (;;)
      {
        if ((ETH->DMABMR & ETH_DMABMR_SR) == 0)
          break;
  
        if (ctl_get_current_time() - t0 > 500)
          return CTL_DEVICE_NOT_RESPONDING;
      }
  
    // Bring up MAC.
    stat = designware_emac_v3_start(self);
    if (stat < CTL_NO_ERROR)
      return stat;
  
    // Allow Ethernet interrupts through.
    (void)ctl_set_priority(ETH_IRQn, 1); // low priority
    (void)ctl_unmask_isr(ETH_IRQn);
  
    return CTL_NO_ERROR;
  }
  
  // ATTENTION -- DMA capability restriction for STM32F4 memory
  //
  // Contiguous 112 Kbyte and 16 Kbyte blocks (total 128 Kbyte) mapped at
  // address 0x2000 0000 and accessible by all AHB masters.
  //
  // On STM32F42/3, a 64 Kbyte block mapped at address 0x2002 0000
  // and accessible by all AHB masters.
  //
  // A 64 Kbyte block mapped at address 0x1000 0000 and accessible
  // only by the CPU through the D-bus
  
  
  // Use RAM for Ethernet packets.
  extern char __RAM_segment_start__[];
  extern char __RAM_segment_used_end__[];
  extern char __RAM_segment_end__[];
  
  void
  ETH_IRQHandler(void)
  {
    ctl_enter_isr();
    designware_emac_v3_isr(ctl_net_interface);
    ctl_exit_isr();
  }
  
  CTL_STATUS_t
  platform_configure_network(CTL_NET_INTERFACE_t *nic)
  {
    CTL_STATUS_t stat;
    CTL_NET_MEM_DRIVER_t mem;
  
    // Configure Ethernet pins.
    stat = platform_claim_pin_configuration(emac_configuration);
    if (stat < CTL_NO_ERROR)
      return stat;
  
    // Initialize interface.
    designware_emac_v3_init(nic,
                            ETH,
                            __RAM_segment_used_end__,
                            4,
                            4,
                            stm32_get_clock_frequency(STM32_CLOCK_SOURCE_HCLK));
  
    // Special network setup methods.
    nic->mac.select_phy_fn = ctl_net_autoselect_first_phy_driver;
    nic->mac.init_fn = stm32f4_emac_start;
  
    // Auto-negotiate a connection on RMII.
    ctl_phy_phy_write_auto_configuration(nic, 0, 0);
  
    // Initialize the network heap with left-over AHBSRAM.
    platform_private_init_heaps(&mem,
                                designware_emac_v3_first_free(nic),
                                __RAM_segment_end__ - (char *)designware_emac_v3_first_free(nic));
    ctl_net_set_mem_driver(&mem);
  
    // All done.
    return CTL_NO_ERROR;
  }
  

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