SWD connections for cortex M3 and M4 and the STLIN-V2

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    Michael Johnson

    The latest STM32 CPU support package doesn't use the NSRST pin.

    There are some words in the STM32 manual stating that the debug registers are accessible when the device is in reset. So theoretically the NSRST pin may be used in future to recover devices that have disabled (intentionally or otherwise) the debug port.

    In terms of ARM7/9/11 targets (rather than Cortex-M) targets the prescribed way of getting debug control is to assert NSRST, program the debug registers to break on the reset vector catch and then release NSRST and wait for the vector catch to happen. In practice most ARM7/ARM9's run ROM code out of reset with the debug port disabled so this just doesn't work. We implemented the STARTUP_FROM_RESET game so that when the debugger does assert/release NSRST it can stop the CPU which will be in a known state.

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    Peter Harrison

    Very interesting. Thank you.

    If I understand correctly then, I am safe with the current packages for the Cortex-M devices but the safe bet would be to include the system reset pin in my programming connector?

     

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    Michael Johnson

    I'd leave it connected (but I'd leave the TDI and TDO JTAG pins connected as well).

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    Peter Harrison

    Why would I want those if I can use SWD? Would the possible future use of NSRST also require the use of TDI and TDO?

    My desire is to make best use of board space with simple pin header connections for programming. 

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    Michael Johnson

    If you want to put another jtag device in the chain? Possibly - I haven't done it yet.

    Regards

    Michael

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