Has anyone use a separate PIO pin to control the Chip Select of slave rather than using NPCS? I am using the SPI on AT91sam7se to communicate with an EEPROM, but the EEPROM requires CS pin to be low when 8 bits, 16 bits or 24 bits or data is transferred. I set the SPI transfer 8 bits at a time, and I am using PA1 to work as CS pin. I can see the CS level becomes low when I select the EEPROM and it becomes high when I deselect the EEPROM. But the write_eeprom and read_eeprom is not successful.
Another question is when SPI_Write() operates, do I need to read the SPI_RDR register to avoid overrun error? When I want to read data from EEPROM, after sending the instruction and address, do I need to send a dummy byte 0xFF to initiate the clock and then read the SPI_RDR register to get the reply from EEPROM?
My code for SPI Write is
unsigned char SPI_Write(unsigned int npcs, unsigned char data)
unsigned int temp;
// check if TX register is empty
while ((SPI_SR & SPI_SR_TXEMPTY) == 0);
SPI_TDR = (data) | (npcs << SPI_TDR_PCS_BIT);
while ((SPI_SR & SPI_SR_TDRE_MASK) == 0);
while ((SPI_SR & SPI_SR_RDRF_MASK) == 0);
temp = SPI_RDR;
return (temp & 0xFF);
My understanding is when only doing SPI Write operation, the return temp value is useless, but when the master wants to Read from slave, when sending 0xFF dummy byte, the temp value is what the slave returns.
I am not sure which part is wrong, please give me some idea about the problem. Thanks a lot!
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