CTL task stack
I have looked and find that there is no document that provides a complete explanation of the CTL task stack required sizes based on core architecture and number of tasks and interrupt handlers. I have 9 tasks, using a Cortex M4 core without floating point. I find that each task is using a different number of stack locations based on the CD memory pattern. I also need to know how exactly a stack underflow can occur (or the CD pattern at the bottom of the stack is overwritten). I've used Crossworks as a commercial purchaser for over 35 years and have used CTL 3 or 4 times without problems. It appears that I must have been lucky. Please email or provide all relevant current documentation for CTL and its internal workings so that I can locate and correct a ctl task stack error.
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I have an additional question, I'm using Crossworks for ARM 4.3. Tasking Library 3.6, on a STM32L476 discover board, the ARM-ARCH is V7EM, Core Type is Cortex-M4, FP ABI is soft, FPU is FPv4-SP-D16 all defined from drop down lists in project properties. When I look at CTL_CPU_STATE_WORD_SIZE in ctl.h it is 16 and __ARM_ARCH_FPV4_SP_D16__ is grayed out (not defined). Shouldn't that be defined? if so my CTL_CPU_STATE_WORD_SIZE would be 16+32. Shouldn't the drop down selection of FPv4-SP-D16 have defined it?
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Ok, that's a little bit confusing, especially since I never manually set any of them. I expected that if a core had a hardware FP that it would be enabled by default. All those settings are a result of doing a New CTL project, it would be nice to know what the default setting are for different core types and/or boards.
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